Mathematical implementation of 3GPP TR 38.901 channel models on FPGA hardware for closing velocities up to 300 km/h.
When two vehicles approach each other at 150 km/h on a two-lane road, relative closing speed is 300 km/h, producing carrier frequency offsets of over 1.6 kHz at 5.9 GHz. V2XSim implements tapped delay line (TDL) and clustered delay line (CDL) models in hardware to ensure modem receivers remain synchronized.